A complementary metal-oxide-semiconductor (CMOS) is a core component of a microelectronic integrated circuit, and its size and operating voltage obey the Moore's law, so as to achieve better performance and higher integration density. However, reduction of the size of the CMOS is accompanied with constantly increasing power consumption of the CMOS. One reason is that electric current leakage increases because of a short-channel effect, and the other reason is that it becomes increasingly difficult to reduce supply voltage for the device. The difficulty in reducing supply voltage for the CMOS device mainly results from a relatively large subthreshold swing of the CMOS device, usually higher than 60 mV/dec. A tunnel field-effect transistor (TFET) is considered as a good replacement of the CMOS device for its less electric current leakage and steep subthreshold slope. Currently, when the TFET and a conventional planar structure (such as an MOS transistor, a capacitor, or a resistor) are used to jointly construct a circuit, it is difficult to combine the TFET and the conventional planar structure due to a limitation of a TFET structure characteristic. Currently, to integrate a non-planar TFET and a planar structure, usually a TFET is first formed, the planar structure is formed, and then the TFET and the planar structure are combined. This increases process complexity and implementation costs to a large extent.